Operating speeds of integrated circuits, e.g., "IC chips", are ever increasing. Furthermore, according to another trend, chips with extremely dense circuitry and input and output ("i/o") traffic are being implemented on one chip and are being packaged as high-speed, multi-chip systems. High-speed processor chips are an example of this trend. These developments lead to a need to transmit signals between chips at high speeds.
There is a potential to improve communication and operating speeds by locating chips, and especially their i/o leads, close to one another. However, the layout of these very dense chips and their i/o leads is a very complicated matter, making it difficult to design features in their layout which permit such chips to be packaged close to one another.
As a result, there is a need in the art for improvements in chip and package layout, as well as inter-chip communication methods, in order to address the foregoing needs.